Rockchip DRM RK628 Porting Guide

:::info 文档信息

文档标识：RK-YH-YF-276　·　发布版本：V1.7.0　·　发布日期：2021-05-31　·　页数：44　·　语言：英文

原始文档：Rockchip_DRM_RK628_Porting_Guide_CN.pdf

:::

章节大纲

Rockchip DRM RK628 Porting Guide（P1）
- Introduction（P4）
- Core（P4）
- Input（P5）
  - RGB（P5）
  - BT1120（P6）
  - HDMIRX（P7）
    - HDMIRX 板级直连模式（P7）
    - HDMIRX线缆连接模式（P10）
    - HDMIRX AUDIO（P10）
- Output（P11）
  - Post-Process（P11）
    - Scaler（P12）
    - 极性配置（P13）
  - LVDS（P13）
    - RGB2LVDS（P13）
      - Single LVDS（P13）
      - Dual LVDS（P16）
    - HDMI2LVDS（P16）
      - Single LVDS（P16）
      - Dual LVDS（P19）
  - DSI（P20）
    - RGB2DSI（P20）
      - Single DSI（P20）
      - Dual DSI（P23）
    - HDMI2DSI（P23）
      - Single DSI（P24）
  - HDMITX（P27）
    - RGB2HDMI（P27）
    - BT1120->HDMI（P28）
    - HDMITX Audio（P32）
  - GVI（P32）
    - GVI 说明（P32）
    - 配置说明（P32）
  - MIPI CSI（P37）
    - dts配置（P37）
    - 注意事项（P39）
- DEBUG（P39）
  - I2C通信异常（P39）
  - RK628 PLL 锁定异常（P40）
  - 寄存器读写（P40）
  - 输入输出信息（P41）
    - cat /d/dri/0/summary（P41）
    - cat /d/clk/clk_summary（P42）
  - 主副屏属性配置（P42）
  - 自测模式（P43）
    - HDMITX color bar（P43）
    - DSI color bar（P43）
    - GVI color bar（P43）
  - 行场解析（P43）
    - rk628_bt1120_rx（P43）

在线预览

若预览无法显示，请直接下载 PDF 后用本地阅读器打开。

1. Introduction

本文档主要描述多功能转换芯片RK628的软件配置方法以及调试手段，具体功能描述参考datasheet。

配置项：

CONFIG_MFD_RK628=y
CONFIG_DRM_ROCKCHIP_RK628=y
CONFIG_VIDEO_RK628CSI=y

驱动：

drivers/mfd/rk628.c
drivers/clk/rockchip/regmap/clk-rk628.c
drivers/pinctrl/pinctrl-rk628.c
drivers/gpu/drm/rockchip/rk628/*
drivers/media/i2c/rk628_csi.c

设备树：

arch/arm/boot/dts/rk3288-evb-rk628.dtsi
arch/arm/boot/dts/rk3288-evb-rk628-hdmi2gvi-avb.dtb
arch/arm/boot/dts/rk3288-evb-rk628-hdmi2gvi-avb.dts
arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dtb
arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts
arch/arm/boot/dts/rk3288-evb-rk628-rgb2gvi-avb.dts
arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dtb
arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts
arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-avb.dts
arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-dual-avb.dts
arch/arm/boot/dts/rk3288-evb-rk628-hdmi2csi-avb.dts

2. Core

arch/arm/boot/dts/rk628.dtsi 包含 RK628 相关模块的基础配置，一般不需要更改，只需要在板级 dts中包含该 dtsi。
arch/arm/boot/dts/rk3288-evb-rk628.dtsi 包含特定板级配置，需要根据硬件设计配置 RK628 相关控制IO，并且包含 rk628.dtsi。

&i2c1 {
clock-frequency = <400000>;
rk628: rk628@50 {
reg = <0x50>;
interrupt-parent = <&gpio7>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio7 RK_PB6 GPIO_ACTIVE_LOW>;

3. Input

3.1 RGB

注意：rk3288-android7.1 和 rk3288-android8.1 对应的内核基线 RGB 功能在 dts 中是以 lvds 的节点来描述，在这两个 SDK kernel 中没有关于 rk628 应用方案的配置 dts，可以参考如下相关 dts 配置：RKDocs/PATCHES/patch_rk628_dts_for_rk3288_android8.0.tar.gz

&rgb {
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
&video_phy {
&rgb_in_vopb {
status = "disabled";
&rgb_in_vopl {

3.2 BT1120

arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts

&rgb {
pinctrl-names = "default";
pinctrl-0 = <&bt1120_pins>;
rgb_out_bt1120: endpoint {
remote-endpoint = <&bt1120_in_rgb>;
&rk628_bt1120_rx {
bt1120_in_rgb: endpoint {
remote-endpoint = <&rgb_out_bt1120>;
bt1120_out_post_process: endpoint {
remote-endpoint = <&post_process_in_bt1120>;
&rgb_in_vp2 {

3.3 HDMIRX

HDMIRX 目前支持以下输入源格式：

3840X2160-60Hz(YUV420-8BIT）3840X2160-30Hz(RGB-8BIT) 1920X1080-60Hz(RGB-8BIT) 1280X720-60Hz(RGB-8BIT) 720X576-60Hz(RGB-8BIT) 720X480-60Hz(RGB-8BIT)

3.3.1 HDMIRX 板级直连模式

DTS 配置如下，以 HDMI2GVI 为例：

&hdmi {
hdmi_out_hdmirx: endpoint {
remote-endpoint = <&hdmirx_in_hdmi>;
&panel {
compatible = "simple-panel";
……
display-timings {
native-mode = <&timing>;
timing: timing {
……
port {
panel_in_gvi: endpoint {
remote-endpoint = <&gvi_out_panel>;
&rk628_gvi {
pinctrl-names = "default";
pinctrl-0 = <&gvi_hpd_pins>, <&gvi_lock_pins>;
rockchip,lane-num = <8>;
/* rockchip,division-mode; */
gvi_in_post_process: endpoint {
remote-endpoint = <&post_process_out_gvi>;
gvi_out_panel: endpoint {
remote-endpoint = <&panel_in_gvi>;
&rk628_combtxphy {
&rk628_post_process {
post_process_in_hdmirx: endpoint {
remote-endpoint = <&hdmirx_out_post_process>;
post_process_out_gvi: endpoint {
remote-endpoint = <&gvi_in_post_process>;
&rk628_combrxphy {
&rk628_hdmirx {
hdmirx_in_hdmi: endpoint {
remote-endpoint = <&hdmi_out_hdmirx>;
hdmirx_out_post_process: endpoint {
remote-endpoint = <&post_process_in_hdmirx>;
&hdmi_in_vopl {
status = "disabled";
&hdmi_in_vopb {

注意事项

由于 HDMIRX 最大值支持 4K-60Hz-YUV420，所以当需要输出 4K-60Hz 分辨率时，需要强制限制输入源为 YUV420 颜色格式。必须在输出端限制输入源最大的 TMDS CLK 以及允许 YUV420 格式输出。

以 HDMI2GVI 为例，需要以下修改：

--- a/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c
+++ b/drivers/gpu/drm/rockchip/rk628/rk628_gvi.c
@@ -312,7 +312,8 @@ static int rk628_gvi_connector_get_modes(struct drm_connector
*connector)
info->edid_hdmi_dc_modes = 0;
info->hdmi.y420_dc_modes = 0;
info->color_formats = 0;
-       info->max_tmds_clock = 600000;
+       info->max_tmds_clock = 300000;
+       connector->ycbcr_420_allowed = true;

3.3.2 HDMIRX线缆连接模式

HDMIRX线缆连接模式一般用于HDMIRX to MIPI CSI接口转换，适用于HDMI IN应用场景，支持热拔插、动态分辨率切换等功能。

目前支持以下分辨率，可根据具体项目需求在驱动中继续增加：

3840X2160-30Hz 1920X1080-60Hz 1280X720-60Hz 720X576-50Hz 720X480-60Hz

格式支持：

RGB-8BIT YUV444-8BIT YUV422-8BIT YUV420-8BIT

3.3.3 HDMIRX AUDIO

音频信号通过RK628 I2S输出（RK628必须是master），可以直接连接DAC芯片，或者与SOC的I2S直接连接

与SOC连接时候，RK628 I2S不需要额外的配置，可以使用dummy_codec创建一个声卡设备，供系统使用：

dummy_codec: dummy-codec {
compatible = "rockchip,dummy-codec";
#sound-dai-cells = <0>;
hdmiin-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,hdmiin";
simple-audio-card,bitclock-master = <&dailink0_master>;
simple-audio-card,frame-master = <&dailink0_master>;
simple-audio-card,cpu {
sound-dai = <&i2s0>;
dailink0_master: simple-audio-card,codec {
sound-dai = <&dummy_codec>;

RK3288 EVB使用的是RK3288 I2S与RT5651的I2S2，RK628 I2S与RT5651的I2S2连接。在使用过程中，通过切换RT5651内部的route，达到切换不同通路录音，播放的功能，对应dts配置如下：

hdmiin-sound {
compatible = "rockchip,rockchip-rt5651-rk628-sound";
rockchip,cpu = <&i2s>;
rockchip,codec = <&rt5651>;

注意事项：由于RK628 I2S接口没有提供MCLK，所以如果直接连接DAC的话，最好选择无需MCLK DAC芯片

4. Output

4.1 Post-Process

如图 1-1所示，输入数据需要经过 Post Process 做缩放或是bypass，然后送到各显示接口，所以 dts 必须要配置 rk628_post_process 桥接 RGB 或是 HDMIRX。

以 RGB 为例：

&rgb {
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&vop_pins>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;

4.1.1 Scaler

以 RGB(1080p)-> GVI(4K) 为例，因为 RGB 无法输出4K，所以只能经过 Scaler 做缩放。

因为 GVI 只添加了 4K 的分辨率，在上层 modes 列表中会有 4K 分辨率，但是希望上层设置 1080P(源分辨率) 下来，在 Post Process 再放大到 4K(目标分辨率)，所以需要在 Post Process 添加一个源分辨率，配置如下：

&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&vop_pins>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
post_process_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_post_process>;
+
+   display-timings {
+       native-mode = <&timing0>;
+
+       timing0: timing0 {
+           clock-frequency = <148500000>;
+           hactive = <1920>;
+           vactive = <1080>;
+           hback-porch = <148>;
+           hfront-porch = <88>;
+           vback-porch = <36>;
+           vfront-porch = <4>;
+           hsync-len = <44>;
+           vsync-len = <5>;
+           hsync-active = <0>;
+           vsync-active = <0>;
+           de-active = <0>;
+           pixelclk-active = <0>;
+       };
+   };

4.1.2 极性配置

&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&vop_pins>;
+       mode-sync-pol = <0>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
post_process_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_post_process>;

mode-sync-pol 做为一种规避方法而添加的属性，一般情况不需要配置，只有像 RK3568 RGB 和 LVDS 同时输出的时候，极性没有办法配置，只能输出DRM_MODE_FLAG_NHSYNC/DRM_MODE_FLAG_NVSYNC 的情况下，通过配置 Post Process 的mode-sync-pol 为 0，来适配前级的极性。

4.2 LVDS

4.2.1 RGB2LVDS

4.2.1.1 Single LVDS

arch/arm/boot/dts/rk3288-evb-rk628-rgb2lvds-avb.dts

/ {
panel {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <20>;
enable-delay-ms = <20>;
disable-delay-ms = <20>;
unprepare-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <48000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <90>;
hfront-porch = <90>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <90>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
&rk628_lvds {
lvds_in_post_process: endpoint {
remote-endpoint = <&post_process_out_lvds>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
&rk628_combtxphy {
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&vop_pins>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
post_process_out_lvds: endpoint {
remote-endpoint = <&lvds_in_post_process>;
&rgb {
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
&video_phy {
&rgb_in_vopb {
status = "disabled";
&rgb_in_vopl {
route_rgb {
status = "disabled";

4.2.1.2 Dual LVDS

双 LVDS 输出配置在单 LVDS 配置基础上添加修改 &rk628_lvds 如下属性：

&rk628_lvds {
rockchip,link-type = "dual-link-even-odd-pixels";
...

Property	Value	Comment
rockchip,link-type	dual-link-odd-even-pixels dual-link-even-odd-pixels dual-link-left-right-pixels dual-link-right-left-pixels	双通道 LVDS 需要配置该属性，支持奇偶像素模式和左右像素模式，并且支持数据通道互换。对于左右像素模式，需要在CH0和CH1 上分别接上相同的屏，在配置 timing 时，只需要在单屏 timing 的基础上，将 clock-frequency, hactive, hback-porch, hfront-porch, hsync-len 的值分别x2。

4.2.2 HDMI2LVDS

这种场景， LVDS 分辨率需要将 HDMIRX 支持输入源分辨率因素综合考虑进去。

4.2.2.1 Single LVDS

参考如下配置：

/ {
panel {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <20>;
enable-delay-ms = <20>;
disable-delay-ms = <20>;
unprepare-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <720>;
hback-porch = <220>;
hfront-porch = <110>;
vback-porch = <20>;
vfront-porch = <5>;
hsync-len = <40>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
&rk628_lvds {
lvds_in_post_process: endpoint {
remote-endpoint = <&post_process_out_lvds>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
&rk628_combtxphy {
&rk628_post_process {
post_process_in_hdmirx: endpoint {
remote-endpoint = <&hdmirx_out_post_process>;
post_process_out_lvds: endpoint {
remote-endpoint = <&lvds_in_post_process>;
&rk628_combrxphy {
&rk628_hdmirx {
hdmirx_in_hdmi: endpoint {
remote-endpoint = <&hdmi_out_hdmirx>;
hdmirx_out_post_process: endpoint {
remote-endpoint = <&post_process_in_hdmirx>;
&hdmi {
hdmi_out_hdmirx: endpoint {
remote-endpoint = <&hdmirx_in_hdmi>;
&hdmi_in_vopl {
status = "disabled";
&hdmi_in_vopb {
&route_hdmi {
status = "disabled";

4.2.2.2 Dual LVDS

双 LVDS 输出配置在单 LVDS 配置基础上添加修改 panel timing 和 &rk628_lvds 如下属性：

/ {
panel {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <20>;
enable-delay-ms = <20>;
disable-delay-ms = <20>;
unprepare-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <148500000>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <148>;
hfront-porch = <88>;
vback-porch = <36>;
vfront-porch = <4>;
hsync-len = <44>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
&rk628_lvds {
rockchip,link-type = "dual-link-even-odd-pixels";
...

4.3 DSI

4.3.1 RGB2DSI

4.3.1.1 Single DSI

arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts

&rk628_dsi0 {
dsi0_in_post_process: endpoint {
remote-endpoint = <&post_process_out_dsi0>;
panel@0 {
compatible = "simple-panel-dsi";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
init-delay-ms = <120>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM |
MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 ff 98 81 03
39 00 02 01 00
39 00 02 02 00
...
05 fa 01 11
05 14 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <64000000>;
hactive = <720>;
vactive = <1280>;
hfront-porch = <40>;
hsync-len = <10>;
hback-porch = <40>;
vfront-porch = <22>;
vsync-len = <4>;
vback-porch = <11>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
&rk628_combtxphy {
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&vop_pins>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
post_process_out_dsi0: endpoint {
remote-endpoint = <&dsi0_in_post_process>;
&rgb {
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
&video_phy {
&rgb_in_vopb {
status = "disabled";
&rgb_in_vopl {
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";

4.3.1.2 Dual DSI

在单 Single DSI 的基础上修改如下属性：

&rk628_dsi0 {
...
panel@0 {
compatible = "simple-panel-dsi";
...
dsi,lanes = <8>;
...
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <260000000>;
hactive = <1440>;
vactive = <2560>;
hfront-porch = <150>;
hsync-len = <30>;
hback-porch = <60>;
vfront-porch = <8>;
vsync-len = <4>;
vback-porch = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
&rk628_dsi1 {

4.3.2 HDMI2DSI

这种场景， DSI 分辨率需要将 HDMIRX 支持输入源分辨率因素综合考虑进去。4.3.2.1 Single DSI

arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts

&rk628_dsi0 {
dsi0_in_post_process: endpoint {
remote-endpoint = <&post_process_out_dsi0>;
panel@0 {
compatible = "simple-panel-dsi";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
disable-delay-ms = <120>;
unprepare-delay-ms = <120>;
init-delay-ms = <120>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM |
MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 ff 98 81 03
39 00 02 01 00
39 00 02 02 00
...
05 fa 01 11
05 14 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <720>;
hback-porch = <220>;
hfront-porch = <110>;
vback-porch = <20>;
vfront-porch = <5>;
hsync-len = <40>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
&rk628_combtxphy {
&rk628_post_process {
post_process_in_hdmirx: endpoint {
remote-endpoint = <&hdmirx_out_post_process>;
post_process_out_dsi0: endpoint {
remote-endpoint = <&dsi0_in_post_process>;
&hdmi {
hdmi_out_hdmirx: endpoint {
remote-endpoint = <&hdmirx_in_hdmi>;
&hdmi_in_vopl {
status = "disabled";
&hdmi_in_vopb {
&route_hdmi {
status = "disabled";
&rk628_combrxphy {
&rk628_hdmirx {
hdmirx_in_hdmi: endpoint {
remote-endpoint = <&hdmi_out_hdmirx>;
hdmirx_out_post_process: endpoint {
remote-endpoint = <&post_process_in_hdmirx>;

4.4 HDMITX

4.4.1 RGB2HDMI

arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts

&rk628_hdmi {
hdmi_in_post_process: endpoint {
remote-endpoint = <&post_process_out_hdmi>;
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&vop_pins>;
post_process_in_rgb: endpoint {
remote-endpoint = <&rgb_out_post_process>;
post_process_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_post_process>;
&rgb {
rgb_out_post_process: endpoint {
remote-endpoint = <&post_process_in_rgb>;
&video_phy {
&rgb_in_vopb {
status = "disabled";
&rgb_in_vopl {
&route_rgb {
connect = <&vopl_out_rgb>;
status = "disabled";

4.4.2 BT1120->HDMI

rk3568 平台：arch/arm64/boot/dts/rockchip/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts

#include <arm/rk628.dtsi>
&rk628_hdmi {
hdmi_in_post_process: endpoint {
remote-endpoint = <&post_process_out_hdmi>;
&rk628_post_process {
pinctrl-names = "default";
pinctrl-0 = <&vop_pins>;
mode-sync-pol = <0>;
post_process_in_bt1120: endpoint {
remote-endpoint = <&bt1120_out_post_process>;
post_process_out_hdmi: endpoint {
remote-endpoint = <&hdmi_in_post_process>;
&rk628_bt1120_rx {
bt1120_in_rgb: endpoint {
remote-endpoint = <&rgb_out_bt1120>;
bt1120_out_post_process: endpoint {
remote-endpoint = <&post_process_in_bt1120>;
&rgb {
pinctrl-names = "default";
pinctrl-0 = <&bt1120_pins>;
rgb_out_bt1120: endpoint {
remote-endpoint = <&bt1120_in_rgb>;
&rgb_in_vp2 {

注意事项

HDMITX 最大分辨率支持 1080P60。
HDMITX 需要测试时钟同源的问题，即需要与主控的 RGB 同时钟源，不然会有相位差，导致兼容性问题，比如黑屏/显示黑边等。以 RK3288+RK628 为例，硬件上 RK628 的 24M 时钟需要由RK3288 的 PIN-M23 sclk_testout 提供，软件补丁如下：

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-
rk3288.c
index 2784a7ed05db..68761389b6cf 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -204,6 +204,11 @@ PNAME(mux_hsadcout_p)      = { "hsadc_src", "ext_hsadc"
PNAME(mux_edp_24m_p)   = { "ext_edp_24m", "xin24m" };
PNAME(mux_tspout_p)    = { "cpll", "gpll", "npll", "xin27m" };
+PNAME(mux_testout_src_p) = { "aclk_peri", "clk_core", "aclk_vio0", "ddrphy",
+                            "aclk_vcodec", "aclk_gpu", "rga_core",
"aclk_cpu",
+                            "xin24m", "xin27m", "xin32k", "clk_wifi",
+                            "dclk_vop0", "dclk_vop1", "sclk_isp_jpe",
"sclk_isp" };
+
PNAME(mux_usbphy480m_p)                = { "sclk_otgphy1_480m",
"sclk_otgphy2_480m",
"sclk_otgphy0_480m" };
PNAME(mux_hsicphy480m_p)       = { "cpll", "gpll", "usbphy480m_src" };
@@ -560,6 +565,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
__initdata = {
RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
RK3288_CLKGATE_CON(2), 7, GFLAGS),
+       MUX(SCLK_TESTOUT_SRC, "sclk_testout_src", mux_testout_src_p, 0,
+           RK3288_MISC_CON, 8, 4, MFLAGS),
+       COMPOSITE_NOMUX(SCLK_TESTOUT, "sclk_testout", "sclk_testout_src", 0,
+                       RK3288_CLKSEL_CON(2), 8, 5, DFLAGS,
+                       RK3288_CLKGATE_CON(4), 15, GFLAGS),
+
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
RK3288_CLKGATE_CON(2), 8, GFLAGS),
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-
bindings/clock/rk3288-cru.h
index 1f9c62f07389..61ae793438b4 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -100,6 +100,8 @@
#define SCLK_MAC_PLL           150
#define SCLK_MAC               151
#define SCLK_MACREF_OUT                152
+#define SCLK_TESTOUT_SRC       153
+#define SCLK_TESTOUT           154
#define DCLK_VOP0              190
#define DCLK_VOP1              191
diff --git a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts
b/arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts
index 181ebfdef0ab..0bea70f67a4f 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk628-rgb2hdmi-avb.dts
@@ -39,6 +39,20 @@
+&xin_osc0_func {
+       compatible = "fixed-factor-clock";
+       clocks = <&cru SCLK_TESTOUT>;
+       clock-mult = <1>;
+       clock-div = <1>;
+};
+
+&rk628 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&test_clkout>;
+       assigned-clocks = <&cru SCLK_TESTOUT_SRC>;
+       assigned-clock-parents = <&xin24m>;
+};
&rk628_hdmi {
@@ -114,3 +128,11 @@
connect = <&vopl_out_rgb>;
status = "disabled";
+
+&pinctrl {
+       test {
+               test_clkout: test-clkout {
+                       rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
+               };
+       };
+};

如果是 RK3399+RK628 平台，硬件上 RK628 的 24M 时钟需要由 RK3399 的 PIN-U28 clk_testout2 提供，软件补丁参考 HDMI2GVI 章节。

4.4.3 HDMITX Audio

HDMITX 模式下, HDMI音频数据是通过RK628 I2S接收的，需要与SOC的I2S连接，并配置好声卡供系统调用。如下，RK628 I2S与SOC的I2S0连接：

hdmi_sound: hdmi-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "hdmi-sound";
simple-audio-card,cpu {
sound-dai = <&i2s0>;
simple-audio-card,codec {
sound-dai = <&rk628_hdmi>;

4.5 GVI

4.5.1 GVI 说明

GVI (General Video Interface) 是一种用于视频信号高速传输的通用接口，采用 8B/10B 编码技术和 CDR架构，支持 one-setcion/non-division、two-secion/2 division 模式，传输带宽为 3.75Gbps/lane，最大可以支持 8lane 3840x2160P60 输出。

4.5.2 配置说明

divison 模式配置

GVI 默认为 one section 模式，对于 two section 模式的屏可以通过在 dts 中加入如下属性打开

&rk628_gvi {
rockchip,division-mode;
}

不同模式数据传输方式2. DTS 通路配置demo

RGB2GVI

可以参考 dts demo：arch/arm/boot/dts/rk3288-evb-rk628-rgb2gvi-avb.dts

HDMI2GVI

可以参考 dts demo：arch/arm/boot/dts/rk3288-evb-rk628-hdmi2gvi-avb.dts

如下是 rk3399 平台 HDMI2GVI 软件修改补丁：

/ {
+       panel_gvi {
+               compatible = "simple-panel";
+               //backlight = <&backlight>;
+               power-supply = <&vcc_lcd>;
+               prepare-delay-ms = <20>;
+               //enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+               enable-delay-ms = <200>;
+               disable-delay-ms = <20>;
+               unprepare-delay-ms = <20>;
+               bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
+               width-mm = <136>;
+               height-mm = <217>;
+               status = "okay";
+
+               display-timings {
+                       native-mode = <&timing>;
+
+                       timing: timing {
+                               clock-frequency = <594000000>;
+                               hactive = <3840>;
+                               vactive = <2160>;
+                               hback-porch = <296>;
+                               hfront-porch = <176>;
+                               vback-porch = <72>;
+                               vfront-porch = <8>;
+                               hsync-len = <88>;
+                               vsync-len = <10>;
+                               hsync-active = <1>;
+                               vsync-active = <1>;
+                               de-active = <0>;
+                               pixelclk-active = <0>;
+                       };
+               };
+
+               port {
+                       panel_in_gvi: endpoint {
+                               remote-endpoint = <&gvi_out_panel>;
+                       };
+               };
+       };
+&i2c7 {
+   clock-frequency = <400000>;
+   status = "okay";
+
+   rk628: rk628@50 {
+       reg = <0x50>;
+       interrupt-parent = <&gpio2>;
+       interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
+       //enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+       pinctrl-0 = <&rk628_rst>;
+       pinctrl-names = "default";
+       status = "okay";
+   };
+};
+
+#include <arm/rk628.dtsi>
+
+&hdmi {
+   status = "okay";
+
+   ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       port@1 {
+           reg = <1>;
+
+           hdmi_out_hdmirx: endpoint {
+               remote-endpoint = <&hdmirx_in_hdmi>;
+           };
+       };
+   };
+};
+
+&rk628_gvi {
+   pinctrl-names = "default";
+   pinctrl-0 = <&gvi_hpd_pins>, <&gvi_lock_pins>;
+   status = "okay";
+   rockchip,lane-num = <8>;
+   /* rockchip,division-mode; */
+
+   ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       port@0 {
+           reg = <0>;
+
+           gvi_in_post_process: endpoint {
+               remote-endpoint = <&post_process_out_gvi>;
+           };
+       };
+
+       port@1 {
+           reg = <1>;
+
+           gvi_out_panel: endpoint {
+               remote-endpoint = <&panel_in_gvi>;
+           };
+       };
+   };
+};
+
+&rk628_combtxphy {
+   status = "okay";
+};
+
+&rk628_post_process {
+   status = "okay";
+
+   ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       port@0 {
+           reg = <0>;
+
+           post_process_in_hdmirx: endpoint {
+               remote-endpoint = <&hdmirx_out_post_process>;
+           };
+       };
+
+
+       port@1 {
+           reg = <1>;
+
+           post_process_out_gvi: endpoint {
+               remote-endpoint = <&gvi_in_post_process>;
+           };
+       };
+   };
+};
+
+&rk628_combrxphy {
+   status = "okay";
+};
+
+&rk628_hdmirx {
+   status = "okay";
+
+   ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       port@0 {
+           reg = <0>;
+
+           hdmirx_in_hdmi: endpoint {
+               remote-endpoint = <&hdmi_out_hdmirx>;
+           };
+       };
+       port@1 {
+           reg = <1>;
+
+           hdmirx_out_post_process: endpoint {
+               remote-endpoint = <&post_process_in_hdmirx>;
+           };
+       };
+   };
+};
&pinctrl {
+   rk628_gpio {
+       rk628_rst: rk628_rst {
+           rockchip,pins = <3 16 RK_FUNC_GPIO &pcfg_pull_none>;
+       };
+   };
+
+   test {
+       clk_testout2: clk_testout2 {
+           rockchip,pins = <0 8 RK_FUNC_3 &pcfg_pull_none>;
+       };
+   };

/* rk3399 控制器提供的24MHz同源修改如下 */

+&xin_osc0_func {
+       compatible = "fixed-factor-clock";
+       clocks = <&cru SCLK_TESTCLKOUT2>;
+       clock-mult = <1>;
+       clock-div = <1>;
+};
+
+&rk628: rk628@50 {
+   pinctrl-0 = <&rk628_rst>, <&clk_testout2>;
+   pinctrl-names = "default";
+   assigned-clocks = <&cru SCLK_TESTCLKOUT2>;
+   assigned-clock-rates = <24000000>;
+};
+

4.6 MIPI CSI

MIPI CSI用于HDMIRX to MIPI CSI接口转换，适用于HDMI IN应用场景。HDMI IN详细开发指南可参考SDK文档：

RKDocs/common/hdmi-in/Rockchip_Developer_Guide_HDMI_IN_Based_On_CameraHal3_CN.pdf

或从redmine获取：

https://redmine.rock-chips.com/documents/53

4.6.1 dts配置

dts配置与MIPI SOC Camera类似，涉及到相关硬件连接，请根据实际项目修改，以rk3288平台为例：

hpd-output-inverted：HPD输出取反配置，若HPD输出电平在电路上做了取反，则需要使能此配置项。2. plugin-det-gpios：用于检测HDMI接口上的5V状态，即检测HDMI线缆是否插入。3. power-gpios：用于RK AP端（如RK3288/RK3399）的MIPI CSI接口电源域供电控制，若为常供电，可不配置。

&rk628_combrxphy {
&rk628_combtxphy {
&rk628_csi {
/*
* If the hpd output level is inverted on the circuit,
* the following configuration needs to be enabled.
*/
/* hpd-output-inverted; */
plugin-det-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "RK628-CSI";
rockchip,camera-module-lens-name = "NC";
port {
hdmiin_out0: endpoint {
remote-endpoint = <&mipi_in>;
data-lanes = <1 2 3 4>;
&mipi_phy_rx0 {
mipi_in: endpoint@1 {
remote-endpoint = <&hdmiin_out0>;
data-lanes = <1 2 3 4>;
dphy_rx_out: endpoint@0 {
remote-endpoint = <&isp_mipi_in>;
&rkisp1 {
port {
isp_mipi_in: endpoint@0 {
remote-endpoint = <&dphy_rx_out>;

4.6.2 注意事项

RK AP端对MIPI CSI数据接收部分，类似于camera sensor v4l2驱动，可使用media-ctl、v4l2-ctl工具来调试。2. HDMI IN应用场景，接收3840X2160-30Hz时，MIPI速率较高，ISP频率需要达到625MHz或以上，部分芯片平台（如RK3399）需要修改时钟树配置，使ISP能够获取到需要的频点，同时ISP驱动中需要增加配置对应的频点。以RK3288/RK3399为例，ISP驱动相关代码在：

drivers/media/platform/rockchip/isp1/dev.c

当HDMI IN为3840X2160-30Hz时，根据实际系统负载，可能会存在带宽不足导致丢帧或MIPI接收异常等问题，此时需要提高DDR频率，若仍无改善，可给ISP预留使用CMA内存，以解决此问题。

在rockchip_defconfig配置预留CMA内存128MB

CONFIG_CMA=y
CONFIG_CMA_SIZE_MBYTES=128

在dts配置ISP关闭IOMMU，使用CMA内存

&isp_mmu {
status = "disabled";

5. DEBUG

5.1 I2C通信异常

如下log表示RK628的I2C通信异常导致RK628的各个模块注册不上，需要检查RK628的时序以及24MHz的基准时钟，以及相关pin的iomux。

...
[    0.960609] rk628 1-0050: failed to access register: -6
...
[    1.137516] [drm] Rockchip DRM driver version: v1.0.1
[    1.137982] rockchip-drm display-subsystem: devfreq is not set
[    1.139225] rockchip-drm display-subsystem: bound ff930000.vop (ops
vop_component_ops)
[    1.140167] rockchip-drm display-subsystem: bound ff940000.vop (ops
vop_component_ops)
[    1.140707] dwhdmi-rockchip ff980000.hdmi: registered DesignWare HDMI I2C bus
driver
[    1.140838] dwhdmi-rockchip ff980000.hdmi: Detected HDMI TX controller v2.01a
with HDCP (DWC HDMI
2.0 TX PHY)
[    1.141198] dwhdmi-rockchip ff980000.hdmi: can't find next bridge
[    1.141563] rockchip-drm display-subsystem: failed to bind ff980000.hdmi (ops
dw_hdmi_rockchip_ops): -517
[    1.141942] rockchip-drm display-subsystem: master bind failed: -517
[    1.142933] rockchip-dmc dmc: Get drm_device fail

5.2 RK628 PLL 锁定异常

如下log表示RK628 的 cpll 处于未 lock 状态，按如下步骤排查：

1、24MHz 时钟的电压是否符合预期设计；2、i2c bus 下面是否有和 rk628 同一设备地址的其他硬件设备，干扰 i2c 的通信；

...
rk628-cru rk628-cru: rk628_clk_cpll is not lock
...

5.3 寄存器读写

寄存器调试节点：

console:/ # ls /d/regmap/
0-001b           1-0050-dsi0          2-001a             rk628-dsi0-phy
1-0050-combtxphy 1-0050-grf           ff890000.i2s
1-0050-cru       1-0050-rk628-pinctrl ff96c000.video-phy

寄存器节点默认只读，如果需要寄存器可写，需要添加如下修改：

diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-
debugfs.c
index 3f0a7e262d69..b819645edd84 100644
--- a/drivers/base/regmap/regmap-debugfs.c
+++ b/drivers/base/regmap/regmap-debugfs.c
@@ -259,7 +259,7 @@ static ssize_t regmap_map_read_file(struct file *file, char
__user *user_buf,
count, ppos);
}
-#undef REGMAP_ALLOW_WRITE_DEBUGFS
+#define  REGMAP_ALLOW_WRITE_DEBUGFS
#ifdef REGMAP_ALLOW_WRITE_DEBUGFS
/*
* This can be dangerous especially when we have clients such as

读寄存器

console:/ # cat /d/regmap/1-0050-grf/registers
000: 0600062b
004: ffffffff
008: 00000000
00c: 00000000
010: 00000001
014: 00000000
018: 00050000
01c: 000a032a
020: 00320302
…

写寄存器

console:/ # echo 0x000 0xffffffff > /d/regmap/1-0050-grf/registers

5.4 输入输出信息

5.4.1 cat /d/dri/0/summary

console:/ # cat /d/dri/0/summary
VOP [ff930000.vop]: DISABLED
VOP [ff940000.vop]: ACTIVE
Connector: DPI
overlay_mode[0] bus_format[100a] output_mode[0] color_space[0]
Display mode: 720x1280p60
clk[64000] real_clk[64000] type[8] flag[5]
H: 720 760 770 810
V: 1280 1302 1306 1317
win0-0: ACTIVE
format: AB24 little-endian (0x34324241) SDR[0] color_space[0]
csc: y2r[0] r2r[0] r2y[0] csc mode[0]
zpos: 0
src: pos[0x0] rect[720x1280]
dst: pos[0x0] rect[720x1280]
buf[0]: addr: 0x00384000 pitch: 2880 offset: 0
win1-0: DISABLED
win2-0: DISABLED
win2-1: DISABLED
win2-2: DISABLED
win2-3: DISABLED
win3-0: DISABLED
win3-1: DISABLED
win3-2: DISABLED
win3-3: DISABLED
post: sdr2hdr[0] hdr2sdr[0]
pre : sdr2hdr[0]
post CSC: r2y[0] y2r[0] CSC mode[1]

5.4.2 cat /d/clk/clk_summary

root@rk3288:/ # cat /d/clk/clk_summary | grep rk628
rk628_clk_gpio_db3          0           0            24000000
rk628_clk_gpio_db2          0           0            24000000
rk628_clk_gpio_db1          0           0            24000000
rk628_clk_gpio_db0          0           0            24000000
rk628_clk_hdmirx_cec        0           0            39331
rk628_clk_txesc             0           0            24000000
rk628_clk_cfg_dphy1         0           0            24000000
rk628_clk_cfg_dphy0         1           1            24000000
rk628_clk_gpll              0           0            983039999
rk628_clk_gpll_mux       0           0            983039999
rk628_clk_i2s_8ch_src 0           0            98304000
rk628_mclk_i2s_8ch 0           0            98304000
rk628_clk_i2s_8ch_frac 0           0            3736462
rk628_clk_hdmirx_aud  0           0            98304000
rk628_clk_cpll              1           1            1188000000
rk628_clk_cpll_mux       3           3            1188000000
rk628_clk_bt1120dec   0           0            148500000
rk628_pclk_logic      3           7            99000000
rk628_pclk_gpio0   0           1            99000000
rk628_pclk_gpio1   0           1            99000000
rk628_pclk_gpio2   0           1            99000000
rk628_pclk_gpio3   0           1            99000000
rk628_pclk_txphy_con 1           1            99000000
rk628_pclk_efuse   0           0            99000000
rk628_pclk_i2c2apb 0           0            99000000
rk628_pclk_cru     0           0            99000000
rk628_pclk_adapter 0           0            99000000
rk628_pclk_regfile 0           0            99000000
rk628_pclk_dsi0    1           1            99000000
rk628_pclk_dsi1    0           0            99000000
rk628_pclk_csi     0           0            99000000
rk628_pclk_hdmitx  0           0            99000000
rk628_pclk_rxphy   0           0            99000000
rk628_pclk_hdmirx  0           0            99000000
rk628_pclk_gvihost 0           0            99000000
rk628_sclk_vop        1           1            64000000
rk628_clk_rx_read     1           1            64000000
rk628_clk_imodet      0           0            49500000
rk628_i2s_mclkout        0           0            12000000

5.5 主副屏属性配置

以 RGB2DSI 为例，DPI 表示输入为 RGB，DSI 表示输出为 DSI。当需要配置主副屏属性时，应根据输出的对应类型进行配置。

console:/ # ls /sys/class/drm/
card0 card0-DSI-1 controlD64 renderD128 version

属性配置如下：

sys.hwc.device.primary=DSI

Android9.0 以上：

vendor.hwc.device.primary=DSI

5.6 自测模式

在调试过程中，可以通过以下命令测试输出模块的控制器、对应的 phy、屏端这条链路是否正常工作，如果 color bar 能正常显示，请检查主控输出、RK628 input、RK628 Process 的配置，反之请检查对应输出接口和屏端的配置：

5.6.1 HDMITX color bar

echo 0x70324 0x00 > /d/regmap/1-0050-hdmi/registers
echo 0x70324 0x40 > /d/regmap/1-0050-hdmi/registers

5.6.2 DSI color bar

echo 0x50038 0x13f02 > /d/regmap/1-0050-dsi0/registers

5.6.3 GVI color bar

echo  0x80060 0x1 > /d/regmap/1-0050-gvi/registers

5.7 行场解析

5.7.1 rk628_bt1120_rx

通过如下命令可以判断 rk628_bt1120_rx 解析到行场是否正确：

cat /d/regmap/1-0051-grf/registers | grep 12c
[28:16]:Decoder 1120 last line_number of Y
[12:0]:Decoder 1120 last line_number of CbCr
cat /d/regmap/1-0051-grf/registers | grep 130
[24:13]:Decoder 1120 last pixel number of Y
[12:0]:Decoder 1120 last pixel number of CbCr

章节大纲​

在线预览​

1. Introduction​

2. Core​

3. Input​

3.1 RGB​

3.2 BT1120​

3.3 HDMIRX​

3.3.1 HDMIRX 板级直连模式​

3.3.2 HDMIRX线缆连接模式​

3.3.3 HDMIRX AUDIO​

4. Output​

4.1 Post-Process​

4.1.1 Scaler​

4.1.2 极性配置​

4.2 LVDS​

4.2.1 RGB2LVDS​

4.2.2 HDMI2LVDS​

4.3 DSI​

4.3.1 RGB2DSI​

4.3.2 HDMI2DSI​

4.4 HDMITX​

4.4.1 RGB2HDMI​

4.4.2 BT1120->HDMI​

4.4.3 HDMITX Audio​

4.5 GVI​

4.5.1 GVI 说明​

4.5.2 配置说明​

4.6 MIPI CSI​

4.6.1 dts配置​

4.6.2 注意事项​

5. DEBUG​

5.1 I2C通信异常​

5.2 RK628 PLL 锁定异常​

5.3 寄存器读写​

5.4 输入输出信息​

5.4.1 cat /d/dri/0/summary​

5.4.2 cat /d/clk/clk_summary​

5.5 主副屏属性配置​

5.6 自测模式​

5.6.1 HDMITX color bar​

5.6.2 DSI color bar​

5.6.3 GVI color bar​

5.7 行场解析​

5.7.1 rk628_bt1120_rx​